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ltc6403-1 1 64031fa typical application features applications description 200mhz, low noise, low power fully differential input/output ampli er/driver the ltc ? 6403-1 is a precision, very low noise, low dis- tortion, fully differential input/output ampli? er optimized for 3v to 5v, single supply operation. the ltc6403-1 is unity gain stable. the ltc6403-1 closed-loop bandwidth extends from dc to 200mhz. in addition to the normal un? ltered outputs (+out and Cout), the ltc6403-1 has a built-in 44.2mhz differential single-pole lowpass ? lter and an additional pair of ? ltered outputs (+outf, and Coutf). an input referred voltage noise of 2.8nv/ hz enables the ltc6403-1 to drive state-of-the-art 14- to 18-bit adcs while operating on the same supply voltage, saving system cost and power. the ltc6403-1 maintains its performance for supplies as low as 2.7v. it draws only 10.8ma, and has a hardware shutdown feature which reduces current consumption to 170a. the ltc6403-1 is available in a compact 3mm 3mm 16-pin leadless qfn package and operates over a C40c to 85c temperature range. single-ended input to differential output with common mode level shifting n very low distortion: (2v p-p , 3mhz): C95dbc n fully differential input and output n low noise: 2.8nv/ hz input-referred n 200mhz gain-bandwidth product n built-in clamp: fast overdrive recovery n slew rate: 200v/s n adjustable output common mode voltage n rail-to-rail output swing n input range extends to ground n large output current: 60ma (typ) n dc voltage offset <1.5mv (max) n 10.8ma supply current n 2.7v to 5.25v supply voltage range n low power shutdown n tiny 3mm 3mm 0.75mm 16-pin qfn package n differential input a/d converter driver n single-ended to differential conversion/ampli? cation n common mode level translation n low voltage, low noise, signal processing , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. + 402 3v v ocm 1.5v 0v 64031 ta01 v s 1v p-p 402 0.1 f 392 ltc6403-1 0.01 f 50 signal generator 54.9 422 1.5v 1v p-p 2v p-p frequency (mhz) 1 ?20 distortion (dbc) ?10 ?0 ?0 ?0 10 100 64031 ta01b ?0 ?00 ?0 ?0 ?0 single-ended input v s = 3v v ocm = v icm = 1.5v r f = r i = 402 r load = 800 v outdiff = 2v p-p second third harmonic distortion vs frequency
ltc6403-1 2 64031fa ltc6403-1 dc electrical characteristics absolute maximum ratings total supply voltage (v + to v C ) ................................5.5v input voltage (+in, Cin, v ocm , shdn ) (note 2) ................... v + to v C input current (+in, Cin, v ocm , shdn ) (note 2) .....................10ma output short-circuit duration (note 3) ............ inde? nite operating temperature range (note 4) ............................................... C40c to 85c speci? ed temperature range (note 5) ............................................... C40c to 85c junction temperature ........................................... 150c storage temperature range ................... C65c to 150c (note 1) the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v + = 3v, v C = 0v, v cm = v ocm = v icm = mid-supply, v shdn = open, r i = 402 , r f = 402 , r l = open, r bal = 100k (see figure 1) unless otherwise noted. v s is de? ned as (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v icm is de? ned as (v +in + v Cin )/2. v outdiff is de? ned as (v +out C v Cout ). v indiff is de? ned as (v inp C v inm ). symbol parameter conditions min typ max units v osdiff differential offset voltage (input referred) v s = 2.7v v s = 3v v s = 5v l l l 0.4 0.4 0.4 1.5 1.5 2 mv mv mv v osdiff / t differential offset voltage drift (input referred) v s = 2.7v v s = 3v v s = 5v 1 1 1 v/c v/c v/c pin configuration 16 17 15 14 13 5 6 7 8 top view ud package 16-lead (3mm 3mm) plastic qfn 9 10 11 12 4 3 2 1 shdn v + v v ocm v v + v + v nc +in ?ut ?utf nc ?n +out +outf t jmax = 150c, ja = 160c/w, jc = 4.2c/w exposed pad (pin 17) is v C , must be soldered to pcb order information lead free finish tape and reel part marking* package description specified temperature range ltc6403cud-1#pbf ltc6403iud-1#pbf ltc6403cud-1#trpbf ltc6403iud-1#trpbf ldbm ldbm 16-lead (3mm 3mm) plastic qfn 16-lead (3mm 3mm) plastic qfn 0c to 70c C40c to 85c consult ltc marketing for parts speci? ed with wider operating temperature ranges. *the temperature grade is identi? ed by a label on the shipping container. consult ltc marketing for information on non-standard lead based ? nish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/
ltc6403-1 3 64031fa symbol parameter conditions min typ max units i b input bias current (note 6) v s = 2.7v v s = 3v v s = 5v l l l C25 C25 C25 C7.5 C7.5 C7.5 0 0 0 a a a i os input offset current (note 6) v s = 2.7v v s = 3v v s = 5v l l l 0.2 0.2 0.2 5 5 5 a a a r in input resistance common mode differential mode 1.7 14 m k c in input capacitance differential mode 1 pf e n differential input referred noise voltage density f = 1mhz 2.8 nv/ i n input noise current density f = 1mhz 1.8 pa/ e nvocm input referred common mode output noise voltage density f = 1mhz, v ocm shorted to ground, v + = 1.5v, v C = C1.5v 17 nv/ ? h ? z v icmr input signal common mode range (note 7) v s = 3v v s = 5v l l 0 0 1.6 3.6 v v cmrri input common mode rejection ratio (input referred) v icm / v osdiff (note 8) v s = 3v, v icm = 0.75v v s = 5v, v icm = 1.25v l l 50 50 72 72 db db cmrrio output common mode rejection ratio (input referred) v ocm / v osdiff (note 8) v s = 5v, v ocm = 2v l 50 90 db psrr differential power supply rejection ( v s / v osdiff ) (note 9) v s = 2.7v to 5.25v l 60 97 db psrrcm output common mode power supply rejection ( v s / v oscm ) (note 9) v s = 2.7v to 5.25v l 45 63 db g cm common mode gain ( v outcm / v ocm )v s = 5v, v ocm = 2v l 1v/v g cm common mode gain error (100 ? (g cm C 1)) v s = 5v, v ocm = 2v l C0.4 C0.1 0.3 % bal output balance ( v outcm / v outdiff ) v outdiff = 2v single-ended input differential input l l C63 C66 C45 C45 db db v oscm common mode offset voltage (v outcm C v ocm )v s = 2.7v v s = 3v v s = 5v l l l 10 10 10 25 25 25 mv mv mv v oscm / t common mode offset voltage drift v s = 2.7v v s = 3v v s = 5v 20 20 20 v/c v/c v/c v outcmr output signal common mode range (voltage range for the v ocm pin) (note 7) v s = 3v v s = 5v l l 1.1 1.1 2 4 v v r invocm input resistance, v ocm pin l 15 23 32 k v ocm voltage at the v ocm pin (self-biased) v s = 3v, v ocm = open l 1.45 1.5 1.55 v v out output voltage, high, either output pin (note 10) v s = 3v, i l = 0 v s = 3v, i l = 5ma v s = 3v, i l = 20ma l l l 190 190 340 300 300 490 mv mv mv v s = 5v, i l = 0 v s = 5v, i l = 5ma v s = 5v, i l = 20ma l l l 170 195 380 300 340 550 mv mv mv ltc6403-1 dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v + = 3v, v C = 0v, v cm = v ocm = v icm = mid-supply, v shdn = open, r i = 402 , r f = 402 , r l = open, r bal = 100k (see figure 1) unless otherwise noted. v s is de? ned as (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v icm is de? ned as (v +in + v Cin )/2. v outdiff is de? ned as (v +out C v Cout ). v indiff is de? ned as (v inp C v inm ).
ltc6403-1 4 64031fa symbol parameter conditions min typ max units v out output voltage, low, either output pin (note 10) v s = 3v, i l = 0 v s = 3v, i l = C5ma v s = 3v, i l = C20ma l l l 150 165 210 220 245 300 mv mv mv v s = 5v, i l = 0 v s = 5v, i l = C5ma v s = 5v, i l = C20ma l l l 165 175 225 265 275 350 mv mv mv i sc output short-circuit current, either output pin (note 11) v s = 2.7v v s = 3v v s = 5v l l l 30 30 35 58 60 74 ma ma ma a vol large-signal voltage gain v s = 3v 90 db v s supply voltage range l 2.7 5.25 v i s supply current v s = 2.7v v s = 3v v s = 5v l l l 10.7 10.8 11 11.8 11.8 12.1 ma ma ma i shdn supply current in shutdown v s = 2.7v v s = 3v v s = 5v l l l 0.16 0.17 0.26 0.5 0.5 1 ma ma ma v il shdn input logic low v s = 2.7v to 5v l v + C 2.1 v v ih shdn input logic high v s = 2.7v to 5v l v + C 0.6 v r shdn shdn pull-up resistor v s = 5v, v shdn = 2.9v to 0v 40 66 90 k t on turn-on time v s = 3v, v shdn = 0.5v to 3v 4s t off turn-off time v s = 3v, v shdn = 3v to 0.5v 350 ns the denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v + = 3v, v C = 0v, v cm = v ocm = v icm = mid-supply, v shdn = open, r i = 402 , r f = 402 , r t = 25.5 , unless otherwise noted (see figure 2). v s is de? ned (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v icm is de? ned as (v +in + v Cin )/2. v outdiff is de? ned as (v +out C v Cout ). v indiff is de? ned as (v inp C v inm ). ltc6403-1 ac electrical characteristics symbol parameter conditions min typ max units t ovdr output overdrive recovery no glitches 70 ns sr slew rate v s = 3v v s = 5v 200 200 v/s v/s gbw gain-bandwidth product v s = 3v v s = 5v 200 200 mhz mhz f 3db C3db frequency (see figure 2) v s = 3v v s = 5v l l 100 100 200 200 mhz mhz hd2 hd3 3mhz distortion v s = 3v, v outdiff = 2v p-p single-ended input 2nd harmonic 3rd harmonic C97 C95 dbc dbc hd2 hd3 3mhz distortion v s = 3v, v outdiff = 2v p-p differential input 2nd harmonic 3rd harmonic C106 C94 dbc dbc ltc6403-1 dc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v + = 3v, v C = 0v, v cm = v ocm = v icm = mid-supply, v shdn = open, r i = 402 , r f = 402 , r l = open, r bal = 100k (see figure 1) unless otherwise noted. v s is de? ned as (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v icm is de? ned as (v +in + v Cin )/2. v outdiff is de? ned as (v +out C v Cout ). v indiff is de? ned as (v inp C v inm ).
ltc6403-1 5 64031fa note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the inputs +in, Cin are protected by a pair of back-to-back diodes. if the differential input voltage exceeds 1.4v, the input current should be limited to less than 10ma. input pins (+in, Cin, v ocm , and shdn ) are also protected by steering diodes to either supply. if the inputs should exceed either supply voltage, the input current should be limited to less than 10ma. note 3: a heat sink may be required to keep the junction temperature below the absolute maximum rating when the output is shorted inde? nitely. long term application of output currents in excess of the absolute maximum ratings may impair the life of the device. note 4: the ltc6403-1 is guaranteed functional over the operating temperature range C40c to 85c. note 5: the ltc6403c-1 is guaranteed to meet speci? ed performance from 0c to 70c. the ltc6403c-1 is designed, characterized, and expected to meet speci? ed performance from C40c to 85c but is not tested or qa sampled at these temperatures. the ltc6403i-1 is guaranteed to meet speci? ed performance from C40c to 85c. note 6: input bias current is de? ned as the average of the input currents ? owing into pin 6 and pin 15 (Cin, and +in). input offset current is de? ned as the difference of the input currents ? owing into pin 15 and pin 6 (i os = i b + C i b C ) note 7: input common mode range is tested using the test circuit of figure 1 by measuring the differential gain with a 1v differential output with v icm = mid-supply, and also with v icm at the input common mode range limits listed in the electrical characteristics table, verifying that the differential gain has not deviated from the mid supply common mode input case by more than 1%, and the common mode offset (v oscm ) has not deviated from the mid-supply case by more than 10mv. the voltage range for the output common mode range is tested using the test circuit of figure 1 by applying a voltage on the v ocm pin and testing at both mid supply and at the electrical characteristics table limits to verify that the differential gain has not deviated from the mid supply v ocm case by more than 1%, and the common mode offset (v oscm ) has not deviated by more than 10mv from the mid supply case. note 8: input cmrr is de? ned as the ratio of the change in the input common mode voltage at the pins +in or Cin to the change in differential input referred voltage offset. output cmrr is de? ned as the ratio of the change in the voltage at the v ocm pin to the change in differential input referred voltage offset. these speci? cations are strongly dependent on feedback ratio matching between the two outputs and their respective inputs, and it is dif? cult to measure actual ampli? er performance. see the effects of resistor pair mismatch in the applications information section of this datasheet. for a better indicator of actual ampli? er performance independent of feedback component matching, refer to the psrr speci? cation. note 9: differential power supply rejection (psrr) is de? ned as the ratio of the change in supply voltage to the change in differential input referred voltage offset. common mode power supply rejection (psrrcm) is de? ned as the ratio of the change in supply voltage to the change in the common mode offset, v outcm C v ocm . note 10: output swings are measured as differences between the output and the respective power supply rail. note 11: extended operation with the output shorted may cause junction temperatures to exceed the 150c limit and is not recommended. see note 3 for more details. note 12: a resistive load is not required when driving an ad converter with the ltc6403-1. therefore, typical output power is very small. in order to compare the ltc6403-1 with ampli? ers that require 50 output load, the ltc6403-1 output voltage swing driving a given r l is converted to oip3 as if it were driving a 50 load. using this modi? ed convention, 2v p-p is by de? nition equal to 10dbm, regardless of actual r l . the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c, v + = 3v, v C = 0v, v cm = v ocm = v icm = mid-supply, v shdn = open, r i = 402 , r f = 402 , r t = 25.5 , unless otherwise noted (see figure 2). v s is de? ned (v + C v C ). v outcm is de? ned as (v +out + v Cout )/2. v icm is de? ned as (v +in + v Cin )/2. v outdiff is de? ned as (v +out C v Cout ). v indiff is de? ned as (v inp C v inm ). ltc6403-1 ac electrical characteristics symbol parameter conditions min typ max units imd third-order imd at 10mhz f1 = 9.5mhz, f2 = 10.5mhz v s = 3v, v outdiff = 2v p-p envelope C72 dbc oip3 equivalent oip3 at 3mhz (note 12) v s = 3v 48 dbm t s settling time 2v step at output v s = 3v, single-ended input 1% settling 0.1% settling 20 30 ns ns nf noise figure, f = 3mhz r source = 804 , r i = 402 , r f = 402 , v s = 3v r source = 200 , r i = 100 , r f = 402 , v s = 3v 10.8 8.9 db db f 3dbfilter differential filter 3db bandwidth 44.2 mhz
ltc6403-1 6 64031fa frequency (mhz) ?0 gain (db) 40 50 ?0 ?0 30 0 20 10 ?0 0.1 10 100 1000 64031 g08 ?0 1 v s = 3v v ocm = v icm = 1.5v r load = 800 a v = 100 a v = 20 a v = 10 a v = 5 a v = 2 a v = 1 temperature ( c) ?0 differential offset voltage (mv) 0 0.4 100 64031 g01 ?.4 ?.8 ?0 20 60 ?0 0 40 80 0.8 ?.2 0.2 ?.6 0.6 v s = 3v v ocm = 1.5v v icm = 1.5v r i = r f = 402 five typical units temperature ( c) ?60 common mode offset voltage (mv) 0 4 100 64031 g02 ?4 ?8 ?20 20 60 ?40 0 40 80 8 ?2 2 ?6 6 v s = 3v v ocm = 1.5v v icm = 1.5v five typical units supply voltage (v) 0 0 total supply current (ma) 2 4 6 8 10 12 1234 64031 g03 5 v shdn = open t a = ?0 c t a = 25 c t a = 85 c shdn voltage (v) 0 0 total supply current (ma) 2 4 6 8 12 0.5 1.0 1.5 2.0 64031 g04 2.5 3.0 10 v s = 3v t a = ?0 c t a = 25 c t a = 85 c supply voltage (v) 0 250 300 350 4 64031 g05 200 150 123 5 100 50 0 shutdown supply current ( a) t a = ?0 c t a = 25 c t a = 85 c v shdn = v frequency (mhz) 1 ?0 gain (db) ?5 ?0 ? 0 10 100 1000 64031 g06 ?5 ?0 ?5 ?0 5 v s = 3v v ocm = v icm = 1.5v r load = 800 r i = r f = 402 capacitor values are from each output to ground. no series resistors are used. c l = 0pf c l = 3.9pf c l = 10pf typical performance characteristics differential offset voltage vs temperature common mode offset voltage vs temperature supply current vs supply voltage supply current vs shdn voltage shutdown supply current vs supply voltage frequency response vs load capacitance frequency response vs gain a v (v/v) r i ( )r f ( ) 1 402 402 2 402 806 5 402 2k 10 402 4.02k 20 402 8.06k 100 402 40.2k
ltc6403-1 7 64031fa v outdiff (v p-p ) 1 ?20 distortion (dbc) ?10 ?00 ?0 ?0 ?0 ?0 23 45 64031 g11 differential inputs v s = 3v v ocm = v icm = 1.5v r f = r i = 402 r load = 800 f in = 3mhz second third frequency (mhz) 1 ?20 distortion (dbc) ?10 ?0 ?0 ?0 10 100 64031 g12 ?0 ?00 ?0 ?0 ?0 single-ended input v s = 3v v ocm = v icm = 1.5v r f = r i = 402 r load = 800 v outdiff = 2v p-p second third v outdiff (v p-p ) 0 ?20 distortion (dbc) ?10 ?0 ?0 ?0 4 ?0 64031 g14 ?00 2 1 35 ?0 ?0 ?0 single-ended input v s = 3v v ocm = v icm = 1.5v r f = r i = 402 r load = 800 f in = 10mhz second third frequency (hz) 100 1 input voltage noise density (nv/ hz) input current noise density (pa/ hz) 10 100 1 10 100 1k 10k 100k 10m 1m 64031 g17 v s = 3v v icm = 1.5v i n e n frequency (mhz) 0.1 output impedance ( ) 1 10 100 1000 0.1 10 100 1000 64031 g18 0.01 1 v s = 3v r i = r f = 402 frequency (mhz) 1 ?20 distortion (dbc) ?00 ?0 ?0 10 100 64031 g09 ?0 ?10 ?0 ?0 ?0 differential inputs v s = 3v v ocm = v icm = 1.5v r f = r i = 402 r load = 800 v outdiff = 2v p-p hd3 hd2 temperature ( c) ?0 slew rate (v/ s) 200 210 220 0 40 100 64031 g2 1 190 180 170 ?0 ?0 20 60 80 v s = 3v v s = 5v frequency (mhz) 30 cmrr (db) 40 50 60 70 0.1 10 100 1000 64031 g19 20 1 v s = 3v v ocm = 1.5v r i = r f = 402 0.05% feedback network resistors harmonic distortion vs frequency typical performance characteristics harmonic distortion vs output amplitude harmonic distortion vs frequency harmonic distortion vs output amplitude input noise density vs frequency differential output impedance vs frequency cmrr vs frequency differential slew rate vs temperature small signal step response 5ns/div 20mv/div 64031 g22 +out ?ut v s = 3v v ocm = v icm = 1.5v r load = 800 r i = r f = 402 c l = 0pf v in = 180mv p-p , differential
ltc6403-1 8 64031fa 20ns/div 0.2v/div 64031 g23 v s = 3v, r load = 800 v in = 2v p-p differential ?ut +out 50ns/div voltage (v) 2.0 2.5 3.0 64031 g24 1.5 1.0 0.5 0 ?ut +out v s = 3v v ocm = 1.5v typical performance characteristics large signal step response overdrive transient response shdn (pin 1): when shdn is ? oating or directly tied to v + , the ltc6403-1 is in the normal (active) operating mode. when pin 1 is pulled a minimum of 2.1v below v + , the ltc6403-1 enters into a low power shutdown state. see applications information for more details. v + , v C (pins 2, 10, 11 and pins 3, 9, 12): power supply pins. three pairs of power supply pins are provided to keep the power supply inductance as low as possible to prevent any degradation of ampli? er 2nd harmonic performance. it is critical that close attention be paid to supply bypassing. for single supply applications (pins 3, 9 and 12 grounded) it is recommended that high quality 0.1f surface mount ceramic bypass capacitors be placed between pins 2 and 3, between pins 11 and 12, and between pins 10 and 9 with direct short connections. pins 3, 9 and 10 should be tied directly to a low impedance ground plane with minimal routing. for dual (split) power supplies, it is recommended that at least two additional high quality, 0.1f ceramic capacitors are used to bypass pin v + to ground and v C to ground, again with minimal routing. for driving large loads (<200 ), additional bypass capacitance may be needed for optimal performance. keep in mind that small geometry (e.g. 0603) surface mount ceramic capacitors have a much higher self resonant frequency than do leaded capacitors, and perform best in high speed applications. pin functions
ltc6403-1 9 64031fa pin functions v ocm (pin 4): output common mode reference voltage. the voltage on v ocm sets the output common mode voltage level (which is de? ned as the average of the voltages on the +out and Cout pins). the v ocm pin is the midpoint of an internal resistive voltage divider between v + and v C that develops a (default) mid-supply voltage potential to maximize output signal swing. the v ocm pin can be overdriven by an external voltage reference capable of driving the input impedance presented by the v ocm pin. on the ltc6403-1, the v ocm pin has an input resistance of approximately 23k to a mid-supply potential. the v ocm pin should be bypassed with a high quality ceramic bypass capacitor of at least 0.01f, (unless you are using split supplies, then connect directly to a low impedance, low noise ground plane) to minimize common mode noise from being converted to differential noise by impedance mismatches both external and internal to the ic. nc (pins 5, 16): no connection. these pins are not con- nected internally. +out, Cout (pins 7, 14): un? ltered output pins. each ampli? er output is designed to drive a load capacitance of 10pf. this means the ampli? er can drive 10pf from each output to ground or 5pf differentially. larger capacitive loads should be decoupled with at least 25 resistors from each output. +outf, Coutf (pins 8, 13): filtered output pins. these pins have a series 100 resistor connected between the ? ltered and un? ltered outputs and three 12pf capacitors. both +outf, and Coutf have 12pf to v C , plus an additional 12pf differentially between +outf and Coutf. this ? lter creates a differential lowpass pole with a C3db bandwidth of 44.2mhz. +in, Cin (pins 15, 6): noninverting and inverting input pins of the ampli? er, respectively. for best performance, it is highly recommended that stray capacitance be kept to an absolute minimum by keeping printed circuit con- nections as short as possible and stripping back nearby surrounding ground plane away from these pins. exposed pad (pin 17): tie the pad to v C (pins 3, 9, and 12). if split supplies are used, do not tie the pad to ground. block diagram + 1 5 nc 6 ?n 7 +out 8 +outf 16 nc 15 +in 14 ?ut 13 ?utf 2 v + 3 v v + v + v + v + v + v v v + v + 100 12pf 12pf 12pf 66k v 4 v ocm v ocm 12 v 64031 bd 11 v + 10 v + 9 v 100 46k v v v + v v + v v + v v + v v + v v v 46k shdn
ltc6403-1 10 64031fa applications information + 1 shdn 5 6 ?n 7 +out 8 +outf 16 15 +in nc nc 14 ?ut 13 ?utf v ?utf r f v+ outf 2 v + 3 v v + v + v v + v 4 v ocm v shdn v ocm v ocm 12 v 11 v + 10 v + 9 v v v v v 64031 f01 ltc6403-1 shdn 0.1 f 0.01 f v cm r f i l r i r i r bal r bal + v inp + v inm i l v ?n v +in v +out v ?ut v outcm v + 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f figure 1. dc test circuit applications information figure 2. ac test circuit (C3db bw testing) v v v + 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f + 1 shdn 5 6 ?n 7 +out 8 +outf 16 15 +in nc nc 14 ?ut 13 ?utf v ?utf r f v +outf 2 v + 3 v v + v + v v + v 4 v ocm v shdn v ocm v inp v inm v ocm 12 v 11 v + 10 v + 9 v v v 64031 f02 ltc6403-1 shdn 0.1 f 0.01 f 0.1 f 0.1 f 0.1 f 0.1 f r f r i r t r i 340 340 50 m/a-com etc1-1-13 mini-circuits tcm4-19 v ?n v +in v +out v ?ut + v in 50 r t 140 140
ltc6403-1 11 64031fa applications information functional description the ltc6403-1 is a small outline, wide band, low noise, and low distortion fully-differential ampli? er with accurate output phase balancing. the ltc6403-1 is optimized to drive low voltage, single-supply, differential input analog- to-digital converters (adcs). the ltc6403-1s output is capable of swinging rail-to-rail on supplies as low as 2.7v, which makes the ampli? er ideal for converting ground referenced, single-ended signals into v ocm referenced differential signals in preparation for driving low voltage, single-supply, differential input adcs. unlike traditional op amps which have a single output, the ltc6403-1 has two outputs to process signals differentially. this allows for two times the signal swing in low voltage systems when compared to single-ended output ampli? ers. the balanced differential nature of the ampli? er also provides even-order harmonic distortion cancellation, and less susceptibility to common mode noise (like power supply noise). the ltc6403-1 can be used as a single ended input to differential output ampli? er, or as a differential input to differential output ampli? er. the ltc6403-1s output common mode voltage, de? ned as the average of the two output voltages, is independent of the input common mode voltage, and is adjusted by applying a voltage on the v ocm pin. if the pin is left open, an internal resistive voltage divider develops a potential halfway between the v + and v C pin voltages. whenever v ocm is not hard tied to a low impedance ground plane, it is recommended that a high quality ceramic capacitor is used to bypass the v ocm pin to a low impedance ground plane (see layout considerations in this document). the ltc6403-1s internal common mode feedback path forces accurate output phase balancing to reduce even order harmonics, and centers each individual output about the potential set by the v ocm pin. vv vv outcm ocm out out == + + ? 2 the outputs (+out and Cout) of the ltc6403-1 are ca- pable of swinging rail-to-rail. they can source or sink up to approximately 60ma of current. additional outputs (+outf and Coutf) are available that provide ? ltered versions of the +out and Cout outputs. an on-chip single pole rc passive ? lter bandlimits the ? ltered outputs to a C3db frequency of 44.2mhz. the user has a choice of using the un? ltered outputs, the ? ltered outputs, or modifying the ? ltered outputs to adjust the frequency response by adding additional components (see output filter considerations and use section). in applications where the full bandwidth of the ltc6403-1 is desired, the un? ltered outputs (+out and Cout) should be used. the un? ltered outputs +out and Cout are designed to drive 10pf to ground (or 5pf differentially). capacitances greater than 10pf will produce excess peaking, which can be mitigated by placing at least 25 in series with the output. input pin protection the ltc6403-1s input stage is protected against differen- tial input voltages that exceed 1.4v by two pairs of back to back diodes connected in anti-parallel series between +in and Cin (pins 6 and 15). in addition, the input pins have steering diodes to either power supply. if the input pair is over-driven, the current should be limited to under 10ma to prevent damage to the ic. the ltc6403-1 also has steering diodes to either power supply on the v ocm , and shdn pins (pins 4 and 1), and if exposed to voltages which exceed either supply, they too, should be current limited to under 10ma. shdn pin if the shdn pin (pin 1), is pulled 2.1v below the positive supply, the ltc6403-1 will power down. the pin has the thevenin equivalent impedance of approximately 66k to v + . if the pin is left unconnected, an internal pull-up resistor of 150k will keep the part in normal active operation. care should be taken to control leakage currents at this pin to under 1a to prevent inadvertently putting the ltc6403-1 into shutdown. in shutdown, all biasing current sources are shut off, and the output pins, +out and Cout, will each appear as an open collector with a non-linear capacitor in parallel and steering diodes to either supply. because of
ltc6403-1 12 64031fa applications information the non-linear capacitance, the outputs still have the ability to sink and source small amounts of transient current if exposed to signi? cant voltage transients. the inputs (+in and Cin) appear as anti-parallel diodes which can conduct if voltage transients at the input exceed 1.4v. the inputs also have steering diodes to either supply. the turn-on time between the shutdown and active states is typically 4s, and turn-off time is typically 350ns. general ampli? er applications as levels of integration have increased and correspond- ingly, system supply voltages decreased, there has been a need for adcs to process signals differentially in order to maintain good signal to noise ratios. these adcs are typically operated from a single supply voltage which can be as low as 3v (2.7v min), and will have an optimal com- mon mode input range near mid-supply. the ltc6403-1 makes interfacing to these adcs trivial, by providing both single ended to differential conversion as well as common mode level shifting. the front page of this datasheet shows a typical application. referring to figure 1, the gain to v outdiff from v inm and v inp is: vvv r r vv outdiff out out f i inp inm = () + ??? ? note from the above equation, the differential output voltage (v +out C v Cout ) is completely independent of input and output common mode voltages. this makes the ltc6403-1 ideally suited for pre-ampli? cation, level shifting and conversion of single-ended input signals to differential output signals in preparation for driving dif- ferential input adcs. effects of resistor pair mismatch figure 3 shows a circuit diagram with takes into consid- eration that real world resistors will not perfectly match. assuming in? nite open loop gain, the differential output relationship is given by the equation: vvv r r v v outdiff out out f i indiff avg i =+ + ?? ? ? n ncm avg ocm v ?? ? where: r f is the average of r f1 , and r f2 , and r i is the average of r i1 , and r i2 . avg is de? ned as the average feedback factor (or gain) from the outputs to their respective inputs: avg i if i if r rr r rr = + + + ? ? ? ? ? ? 1 2 1 11 2 22 ? ? is de? ned as the difference in feedback factors: = ++ r rr r rr i if i if 2 22 1 11 ? v incm is de? ned as the average of the two input voltages v inp , and v inm (also called the source-referred input com- mon mode voltage): vvv incm inp inm =+ () 1 2 ? and v indiff is de? ned as the difference of the input voltages: v indiff = v inp C v inm figure 3. real world application with feedback resistor pair mismatch v v v + 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f + 1 shdn 5 6 ?n 7 +out 8 +outf 16 15 +in nc nc 14 ?ut 13 ?utf v ?utf r f2 v +outf v ?ut v +out 2 v + 3 v v + v + v v + v 4 v ocm v shdn v vocm v ocm 12 v 11 v + 10 v + 9 v v v 64031 f03 ltc6403-1 shdn 0.1 f 0.01 f r f1 r i2 r i1 + v inp + v inm v ?n v +in
ltc6403-1 13 64031fa applications information when the feedback ratios mismatch ( ? ), common mode to differential conversion occurs. setting the differential input to zero (v indiff = 0), the de- gree of common mode to differential conversion is given by the equation: vvvvv outdiff out out incm ocm avg = () + ??? ? in general, the degree of feedback pair mismatch is a source of common mode to differential conversion of both signals and noise. using 1% resistors or better will mitigate most problems, and will provide about 34db worst case of common mode rejection. using 0.1% resistors will provide about 54db of common mode rejection. a low impedance ground plane should be used as a reference for both the input signal source and the v ocm pin. directly shorting v ocm to this ground or bypassing the v ocm with a high quality 0.1f ceramic capacitor to this ground plane will further mitigate against common mode signals being converted to differential. there may be concern on how feedback ratio mismatch affects distortion. distortion caused by feedback ratio mis- match using 1% resistors or better is negligible. however, in single supply level shifting applications where there is a voltage difference between the input common mode voltage and the output common mode voltage, resistor mismatch can make the apparent voltage offset of the ampli? er appear worse than speci? ed. the apparent input referred offset induced by feedback ratio mismatch is derived from the above equation: v osdiff(apparent) (v incm C v ocm ) ? ? using the ltc6403-1 in a single supply application on a single 5v supply with 1% resistors, and the input common mode grounded, with the v ocm pin biased at mid-supply, the worst case mismatch can induce 25mv of apparent offset voltage. with 0.1% resistors, the worst case appar- ent offset reduces to 2.5mv. input impedance and loading effects the input impedance looking into the v inp or v inm input of figure 1 depends on whether the sources v inp and v inm are fully differential. for balanced input sources (v inp = Cv inm ), the input impedance seen at either input is simply: r inp = r inm = r i for single ended inputs, because of the signal imbalance at the input, the input impedance increases over the bal- anced differential case. the input impedance looking into either input is: rr r r rr inp inm i f if == + ? ? ? ? ? ? ? ? ? ? ? ? 1 1 2 ?? input signal sources with non-zero output impedances can also cause feedback imbalance between the pair of feedback networks. for the best performance, it is recommended that the sources output impedance be compensated. if input impedance matching is required by the source, r1 should be chosen (see figure 4): r rr rr inm s inm s 1 = ? ? according to figure 4, the input impedance looking into the differential amp (r inm ) re? ects the single ended source case, thus: r r r rr inm i f if = + ? ? ? ? ? ? ? ? ? ? ? ? 1 1 2 ?? r2 is chosen to balance r1 || rs: r rr rr is is 2 = + ?
ltc6403-1 14 64031fa applications information input common mode voltage range the ltc6403-1s input common mode voltage (v icm ) is de? ned as the average of the two input voltages, v +in , and v Cin . it extends from v C to 1.4v below v + . for fully differential input applications, where v inp = Cv inm , the input common mode voltage is approximately (refer to figure 5): v vv v r rr v r r icm in in vocm i if cm f = + + ? ? ? ? ? ? + + ? ? ? 2 f fi r + ? ? ? ? ? ? with singled ended inputs, there is an input signal com- ponent to the input common mode voltage. applying only v inp (setting v inm to zero), the input common voltage is approximately: v vv v r rr v r r icm in in vocm i if cm f = + + ? ? ? ? ? ? + + ? ? ? 2 f fi inp f fi r vr rr + ? ? ? ? ? ? + + ? ? ? ? ? ? 2 ? output common mode voltage range the output common mode voltage is de? ned as the aver- age of the two outputs: vv vv outcm vocm out out == + + ? 2 the v ocm pin sets this average by an internal common mode feedback loop. the output common mode range extends from 1.1v above v C to 1v below v + . the v ocm pin sits in the middle of an internal voltage divider which sets the default mid-supply open circuit potential. in single supply applications, where the ltc6403-1 is used to interface to an adc, the optimal common mode input range to the adc is often determined by the adcs reference. if the adc makes a reference available for set- ting the input common mode voltage, it can be directly tied to the v ocm pin, but must be capable of driving the input impedance presented by the v ocm as listed in the electrical characteristics table. this impedance can be assumed to be connected to a mid-supply potential. if an external reference drives the v ocm pin, it should still be bypassed with a high quality 0.01f or higher capacitor to a low impedance ground plane to ? lter any thermal noise and to prevent common mode signals on this pin from being inadvertently converted to differential signals. output filter considerations and use filtering at the output of the ltc6403-1 is often desired to provide either anti-aliasing or improved signal to noise ratio. to simplify this ? ltering, the ltc6403-1 includes an additional pair of differential outputs (+outf and Coutf) which incorporate an internal lowpass ? lter network with a C3db bandwidth of 44.2mhz (figure 6). figure 4. optimal compensation for signal source impedance figure 5. circuit for common mode range v s + + r f r f r i r inm v ocm r s r i r2 = r s || r1 r1 chosen so that r1 || r inm = r s r2 chosen to balance r s || r1 r1 64031 f04 v v v + 0.1 f 0.1 f 0.1 f 0.1 f 0.1 f v cm + 1 shdn 5 6 ?n 7 +out 8 +outf 16 15 +in nc nc 14 ?ut 13 ?utf v ?utf r f v +outf v ?ut v +out 2 v + 3 v v + v + v v + v 4 v ocm v shdn v vocm v ocm 12 v 11 v + 10 v + 9 v v v 64031 f05 ltc6403-1 shdn 0.1 f 0.01 f r f r i r i + v inp + v inm v ?n v +in
ltc6403-1 15 64031fa these pins each have an output impedance of 100 . in- ternal capacitances are 12pf to v C on each ? ltered output, plus an additional 12pf capacitor connected differentially between the two ? ltered outputs. this resistor/capacitor combination creates ? ltered outputs that look like a se- ries 100 resistor with a 36pf capacitor shunting each ? ltered output to ac ground, providing a C3db bandwidth of 44.2mhz, and a noise bandwidth of 69.4mhz. the ? lter cutoff frequency is easily modi? ed with just a few external components. to increase the cutoff frequency, simply add 2 equal value resistors, one between +out and +outf and the other between Cout and Coutf (figure 7). these resistors, in parallel with the internal 100 resistors, lower the overall resistance and therefore increase ? lter bandwidth. for example, to double the ? lter bandwidth, add two external 100 resistors to lower the series ? lter resistance to 50 . the 36pf of capacitance remains unchanged, so ? lter bandwidth doubles. keep in mind, the series resistance also serves to decouple the outputs from load capacitance. the un? ltered outputs of the ltc6403-1 are designed to drive 10pf to ground or 5pf differentially, so care should be taken to not lower the effective impedance between +out and +outf or Cout and Coutf below 25 . to decrease ? lter bandwidth, add two external capacitors, one from +outf to ground, and the other from Coutf to ground. a single differential capacitor connected between applications information +outf and Coutf can also be used, and since it is being driven differentially it will appear at each ? ltered output as a single-ended capacitance of twice the value. to halve the ? lter bandwidth, for example, two 36pf capacitors could be added (one from each ? ltered output to ground). alternatively, one 18pf capacitor could be added between the ? ltered outputs, again halving the ? lter bandwidth. combinations of capacitors could be used as well; a three capacitor solution of 12pf from each ? ltered output to ground plus a 12pf capacitor between the ? ltered outputs would also halve the ? lter bandwidth (figure 8). figure 7. ltc6403-1 filter topology modi? ed for 2x filter bandwidth (2 external resistors) figure 6. ltc6403-1 internal filter topology figure 8. ltc6403-1 filter topology modi? ed for 1/2x filter bandwidth (3 external capacitors) + 7 +out 8 +outf 14 ?ut 13 ?utf 12 v 9 v v v 64031 f06 ltc6403-1 filtered output (44.2mhz) 100 12pf 12pf 12pf 100 + 7 +out 8 +outf 14 ?ut 13 ?utf 12 v 9 v v v 64031 f07 ltc6403-1 filtered output ( 88 .4mhz) 100 100 12pf 12pf 12pf 100 100 + 7 +out 8 +outf 14 ?ut 13 ?utf 12 v 9 v v v 64031 f0 8 ltc6403-1 filtered output (22.1mhz) 100 12pf 12pf 12pf 12pf 12pf 100 12pf
ltc6403-1 16 64031fa noise considerations the ltc6403-1s input referred voltage noise is on the order of 2.8nv/ hz . its input referred current noise is on the order of 1.8pa/ hz . in addition to the noise generated by the ampli? er, the surrounding feedback resistors also contribute noise. a noise model is shown in figure 9. the output noise generated by both the ampli? er and the feedback components is governed by the equation: e e r r ir e no ni f i nf n = + ? ? ? ? ? ? ? ? ? ? ? ? + () + ??? ? 12 2 2 2 r ri f i nrf r r e ?? ? ? ? ? ? ? ? ? ? ? ? ? + 2 2 2 a plot of this equation, and a plot of the noise generated by the feedback components for the ltc6403-1 is shown in figure 10. the ltc6403-1s input referred voltage noise contributes the equivalent noise of a 480 resistor. when the feedback network is comprised of resistors whose values are less than this, the ltc6403-1s output noise is voltage noise dominant (see figure 10.): ee r r no ni f i + ? ? ? ? ? ? ?1 feedback networks consisting of resistors with values greater than about 1k will result in output noise which is resistor noise and ampli? er current noise dominant. eir r r ktr no n f f i f () ++ ? ? ? ? ? ? 214 2 ?? ???? lower resistor values (<400 ) always result in lower noise at the penalty of increased distortion due to increased loading of the feedback network on the output. higher applications information figure 9. noise model of the ltc6403-1 + 1 shdn 5 6 ?n 7 +out 8 +outf 16 15 +in nc nc 14 ?ut 13 ?utf e no 2 r f2 2 v + 3 v v + v + v v + v v ocm v ocm 12 v 11 v + 10 v + 9 v v v 64031 f09 ltc6403-1 e nof 2 e nri2 2 shdn r f1 r i2 r i1 v v + v 4 e nrf2 2 e nri1 2 e ncm 2 e ni 2 e nrf1 2 i n +2 i n ?
ltc6403-1 17 64031fa applications information resistor values (but still less than 2k) will result in higher output noise, but improved distortion due to less loading on the output. the optimal feedback resistance for the ltc6403-1 runs between 400 to 2k. the differential ? ltered outputs +outf and Coutf will have a little higher spot noise than the un? ltered outputs (due to the two 100 resistors which contribute 1.3nv/ hz each), but actually will provide superior signal-to-noise ratios in noise bandwidths exceeding 69.4mhz due to the noise-? ltering function the ? lter provides. layout considerations because the ltc6403-1 is a very high speed ampli? er, it is sensitive to both stray capacitance and stray inductance. three pairs of power supply pins are provided to keep the power supply inductance as low as possible to prevent any degradation of ampli? er 2nd harmonic distortion performance. it is critical that close attention be paid to supply bypassing. for single supply applications (pins 3, 9 and 12 grounded) it is recommended that 3 high quality 0.1f surface mount ceramic bypass capacitor be placed between pins 2 and 3, between pins 11and 12, and between pins10 and 9 with direct short connections. pins 3, 9 and 10 should be tied directly to a low impedance ground plane with minimal routing. for dual (split) power supplies, it is recommended that at least two additional high quality, 0.1f ceramic capacitors are used to bypass pin v + to ground and v C to ground, again with minimal routing. for driving large loads (<200 ), additional bypass capacitance may be needed for optimal performance. keep in mind that small geometry (e.g. 0603) surface mount ceramic capacitors have a much higher self resonant frequency than do leaded capacitors, and perform best in high speed applications. any stray parasitic capacitances to ground at the sum- ming junctions +in, and Cin should be kept to an absolute minimum even if it means stripping back the ground plane away from any trace attached to this node. this becomes especially true when the feedback resistor network uses resistor values >2k in circuits with r f = r i . excessive peaking in the frequency response can be mitigated by adding small amounts of feedback capacitance around r f . always keep in mind the differential nature of the ltc6403-1, and that it is critical that the load impedances seen by both outputs (stray or intended) should be as bal- anced and symmetric as possible. this will help preserve the natural balance of the ltc6403-1, which minimizes the generation of even order harmonics, and preserves the rejection of common mode signals and noise. it is highly recommended that the v ocm pin be either hard tied to a low impedance ground plane (in split supply applications), or bypassed to ground with a high quality ceramic capacitor whose value exceeds 0.01f. this will help stabilize the common mode feedback loop as well as prevent thermal noise from the internal voltage divider and other external sources of noise from being converted to differential noise due to divider mismatches in the feed- back networks. it is also recommended that the resistive feedback networks comprise 1% resistors (or better) to enhance the output common mode rejection. this will also prevent the v ocm -referred common mode noise of the common mode ampli? er path (which cannot be ? ltered) from being converted to differential noise, degrading the differential noise performance. figure 10. ltc6403-1 output spot noise vs spot noise contributed by feedback network alone r f = r i ( ) 100 1 nv/ hz 10 100 1k 10k 64031 f10 feedback resistor network noise alone total (amplifier and feedback network) output noise
ltc6403-1 18 64031fa + 1 shdn 5 6 ?n 7 +out 8 +outf 16 15 +in nc nc 14 ?ut 13 ?utf ain + ain 402 2 v + 3 v v + v + v 3.3v v ocm v ocm 12 v 11 v + 10 v + 9 v v v 64031 f11 ltc6403-1 ltc2207 v in , 2v p-p shdn 402 402 402 0.1 f 3.3v 4 0.1 f 0.1 f control gnd v dd d15 d0 0.1 f v cm 2.2 f 3.3v 1 f applications information figure 11. interfacing the ltc6403-1 to adc (shared 3.3v supply voltage) interfacing the ltc6403-1 to a/d converters the ltc6403-1s rail-to-rail output and fast settling time make the ltc6403-1 ideal for interfacing to low voltage, single supply, differential input adcs. the sampling process of adcs creates a sampling glitch caused by switching in the sampling capacitor on the adc front end which momentarily shorts the output of the ampli? er as charge is transferred between the ampli? er and the sampling capacitor. the ampli? er must recover and settle from this load transient before this acquisition period ends for a valid representation of the input signal. in general, the ltc6403-1 will settle much more quickly from these pe- riodic load impulses than from a 2v input step, but it is a good idea to either use the ? ltered outputs to drive the adc (figure 11 shows an example of this), or to place a discrete r-c ? lter network between the differential un? l- tered outputs of the ltc6403-1 and the input of the adc to help absorb the charge injection that comes out of the adc from the sampling process. the capacitance of the ? lter network serves as a charge reservoir to provide high frequency charging during the sampling process, while the two resistors of the ? lter network are used to dampen and attenuate any charge kickback from the adc. the selection of the r-c time constant is trial and error for a given adc, but the following guidelines are recommended: choosing too large of a resistor in the decoupling network will create a voltage divider between the dynamic input impedance of the adc and the decoupling resistors leaving insuf? cient settling time. choosing too small of a resistor will possibly prevent the resistor from properly dampening the load transient caused by the sampling process, prolonging the time required for settling. 16-bit applications require a minimum of 11 r-c time constants to settle. it is rec- ommended that the capacitor chosen have a high quality dielectric (for example, c0g multilayer ceramic).
ltc6403-1 19 64031fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description 3.00 0.10 (4 sides) recommended solder pad pitch and dimensions 1.45 0.05 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation (weed-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 bottom view?exposed pad 1.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 1 pin 1 notch r = 0.20 typ or 0.25 45 chamfer 15 16 2 0.50 bsc 0.200 ref 2.10 0.05 3.50 0.05 0.70 0.05 0.00 ? 0.05 (ud16) qfn 0904 0.25 0.05 0.50 bsc package outline ud package 16-lead plastic qfn (3mm 3mm) (reference ltc dwg # 05-08-1691)
ltc6403-1 20 64031fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2008 lt 0309 rev a ? printed in usa related parts part number description comments high speed differential ampli? ers/differential op amps lt1994 low noise, low distortion differential op amp 16-bit performance at 1mhz, rail-to-rail outputs lt5514 ultralow distortion if ampli? er/adc driver with digitally controlled gain oip3 = 47dbm at 100mhz, gain control range 10.5db to 33db lt5524 low distortion if ampli? er/adc driver with digitally controlled gain oip3 = 40dbm at 100mhz, gain control range 4.5db to 37db ltc6401-20 1.3ghz low noise low distortion differential adc driver a v = 20db, 50ma supply current, imd = C74dbc at 140mhz ltc6401-26 1.6ghz low noise low distortion differential adc driver a v = 26db, 45ma supply current, imd = C72dbc at 140mhz lt6402-6 300mhz differential ampli? er/adc driver a v = 6db, distortion

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